#ifndef __PLATFORM_FH8898__
#define __PLATFORM_FH8898__

#define RAM_BASE			(0x00100000)
#define DDR_BASE			(0x40000000)
#define GICD_REG_BASE		(GIC_REG_BASE+0x1000)
#define GICC_REG_BASE		(GIC_REG_BASE+0x2000)

#define GIC_REG_BASE			(0x00200000)
#define CPU_SYS_APB_REG_BASE	(0x02E00000)
#define DMA0_REG_BASE			(0x08000000)
#define DMA1_REG_BASE			(0x08100000)
#define C2C_INTR0_REG_BASE		(0x08200000)
#define C2C_INTR1_REG_BASE		(0x08300000)
#define TOP_SYS_AHB_REG_BASE	(0x10000000)
#define SPINLOCK_REG_BASE		(0x10C00000)
#define RNG_REG_BASE			(0x10D00000)
#define TOP_SYS_APB_REG_BASE	(0x18000000)
#define UART0_REG_BASE			(0x18200000)
#define UART1_REG_BASE			(0x18300000)
#define UART2_REG_BASE			(0x18400000)
#define UART3_REG_BASE			(0x18500000)
#define UART4_REG_BASE			(0x18600000)
#define UART5_REG_BASE			(0x18700000)
#define RSA_REG_BASE			(0x18D00000)
#define HASH_REG_BASE			(0x18E00000)
#define I2C0_REG_BASE			(0x19700000)
#define I2C1_REG_BASE			(0x19800000)
#define I2C2_REG_BASE			(0x19900000)
#define I2C3_REG_BASE			(0x19A00000)
#define I2C4_REG_BASE			(0x19B00000)
#define I2C5_REG_BASE			(0x19C00000)
#define I2S_REG_BASE			(0x19D00000)
#define TOP_PRE_DIV_RF_REG_BASE	(0x19F00000)
#define TOP_CLK_RF_REG_BASE		(0x19F00200)
#define TOP_CLK_GATE_RF_REG_BASE (0x19F00400)
#define TIMER0_REG_BASE			(0x1A000000)
#define TIMER1_REG_BASE			(0x1A100000)
#define TIMER2_REG_BASE			(0x1A200000)
#define SYS_TIMER_REG_BASE		(0x1A700000)
#define RTC_REG_BASE			(0x1A800000)
#define WDT0_REG_BASE			(0x1A900000)
#define WDT1_REG_BASE			(0x1AA00000)
#define GPIO0_REG_BASE			(0x1B000000)
#define GPIO1_REG_BASE			(0x1B010000)
#define GPIO2_REG_BASE			(0x1B020000)
#define GPIO3_REG_BASE			(0x1B030000)
#define GPIO4_REG_BASE			(0x1B040000)
#define SPI1_REG_BASE			(0x1B700000)
#define SPI2_REG_BASE			(0x1B800000)
#define INT_CTRL0_REG_BASE		(0x1BC00000)
#define INT_CTRL1_REG_BASE		(0x1BD00000)
#define INT_CTRL2_REG_BASE		(0x1BE00000)
#define INT_CTRL3_REG_BASE		(0x1BF00000)
#define PWM_REG_BASE			(0x1C000000)
#define SRC_REG_BASE			(0x1C100000)
#define CEN_GLB_APB_REG_BASE	(0x1CD00000)
#define CEN_PIN_REG_BASE		(0x1D100000)
#define VDU_SYS_PIN_REG_BASE	(0x24000000)
#define VDU_SYS_APB_REG_BASE	(0x24100000)
#define GMAC0_REG_BASE			(0x24700000)
#define GMAC1_REG_BASE			(0x24800000)
#define SADC_REG_BASE			(0x24900000)
#define ACW_REG_BASE			(0x24A00000)
#define REG_EPHY_BASE           (0x24C00000)
#define EFUSE_REG_BASE			(0x25D00000)
#define AES_REG_BASE			(0x26600000)
#define SDC1_REG_BASE			(0x26700000)
#define DMC_SYS_APB_REG_BASE	(0x2C000000)
#define NNP_SYS_PIN_REG_BASE	(0x30000000)
#define NNP_SYS_APB_REG_BASE	(0x30100000)
#define EMMC_PHY_REG_BASE		(0x30700000)
#define SPI0_REG_BASE			(0x30800000)
#define USB3_PHY_REG_BASE		(0x31000000)
#define EMMC_REG_BASE			(0x32100000)
#define SDC0_REG_BASE			(0x32200000)
#define USB2_REG_BASE			(0x32300000)
#define USB3_REG_BASE			(0x32400000)
#define ISP_SYS_PIN_REG_BASE	(0x34000000)
#define ISP_SYS_APB_REG_BASE	(0x34100000)
#define VEU_SYS_AHB_REG_BASE	(0x38100000)
#define PTS_REG_BASE			(0x38900000)

#define REG_PERI_CLK_CTRL		(TOP_SYS_APB_REG_BASE+0x0000)
#define CKG_UART0_EN				(BIT(24))
#define CKG_WDT0_EN					(BIT(7))
#define CKG_XTL_TMR0_EN				(BIT(2))
#define CKG_RTC_TMR0_EN				(BIT(1))
#define CKG_SYST_EN					(BIT(0))

#define REG_PERI_APB_CLK_CTRL	(TOP_SYS_APB_REG_BASE+0x0004)
#define CKG_APB_UART0_EN			(BIT(23))
#define CKG_APB_GPIO_EN				(BIT(22))
#define CKG_APB_WDT0_EN				(BIT(4))
#define CKG_APB_SYST_EN				(BIT(0))

#define CPU_CLK_SEL				(CPU_SYS_APB_REG_BASE+0xc)

#define REG_CPU_SOFT_RST		(CPU_SYS_APB_REG_BASE+0x10)
#define MCU_GLB_SOFT_RST			(BIT(18))
#define MCU_CORE_SOFT_RST			(BIT(17))
#define MCU_ALL_SOFT_RST			(GENMASK(18, 14))

#define REG_CPU_CORE_CTRL		(CPU_SYS_APB_REG_BASE+0x14)
#define CKG_CPU_TS_EN				(BIT(3)) //arch timer
#define CKG_MCU_TS_EN				(BIT(6)) // mcu arch timer

#define REG_DMA_SEL_LOW			(CPU_SYS_APB_REG_BASE+0x10c)
#define REG_DMA_SEL_HIGH		(CPU_SYS_APB_REG_BASE+0x110)
#define REG_DMA0_AXCACHE		(CPU_SYS_APB_REG_BASE+0x1d4)
#define REG_DMA1_AXCACHE		(CPU_SYS_APB_REG_BASE+0x1d8)

#define REG_MCU_ADDR_MSB_SEL	(CPU_SYS_APB_REG_BASE+0x14c)
#define MCU_REMAP					(BIT(4))
#define MCU_AWADDR_SEL				(BIT(3))
#define MCU_ARADDR_SEL				(BIT(2))
#define MCU_MSB_AWADDR				(BIT(1))
#define MCU_MSB_ARADDR				(BIT(0))

#define REG_MCU_START_AWADDR	(CPU_SYS_APB_REG_BASE+0x150)
#define REG_MCU_START_ARADDR	(CPU_SYS_APB_REG_BASE+0x154)
#define REG_COMPARE_AWADDR		(CPU_SYS_APB_REG_BASE+0x158)
#define REG_COMPARE_ARADDR		(CPU_SYS_APB_REG_BASE+0x15c)

#define REG_PMU_CHIP_ID			(CEN_GLB_APB_REG_BASE + 0x0300)
#define REG_PMU_BOOT_MODE		(CEN_GLB_APB_REG_BASE + 0x0308)
#define REG_PMU_DDR_SIZE		(CEN_GLB_APB_REG_BASE + 0x030c)
#define REG_PMU_CHIP_INFO		(CEN_GLB_APB_REG_BASE + 0x0314)
#define REG_PMU_EPHY_PARAM		(CEN_GLB_APB_REG_BASE + 0x0318)
#define REG_PMU_RTC_PARAM		(CEN_GLB_APB_REG_BASE + 0x031c)

#define REG_GLB_RESET			(CEN_GLB_APB_REG_BASE+0xac)
#define SW_GLB_RST					(BIT(0))
#define SW_EXT_RST					(BIT(1))

#define REG_WR_PROTECT			(CEN_GLB_APB_REG_BASE+0xb0)

#define UART_CLOCK_FREQ			24000000    //24M

/*VDU_SYS_APB_REG_BASE + offset ctl efuse cmp func*/
#define EFUSE_CMP_BASE_REG		VDU_SYS_APB_REG_BASE
#define EFUSE_CMP_CTRL0_OFFSET  0x180
#define EFUSE_CMP_CTRL16_OFFSET  0x1c0
#define EFUSE_CMP_CTRL17_OFFSET  0x1c4

#define CKG_TOP_APB_CFG			(TOP_CLK_RF_REG_BASE + 0x30)
#define CKG_GLB_CPU2LVD_CFG		(TOP_CLK_RF_REG_BASE + 0x38)
#define CKG_HASH_CFG			(TOP_CLK_RF_REG_BASE + 0xa8)
#define CKG_RSA_CFG				(TOP_CLK_RF_REG_BASE + 0xb0)

#define NNP_SYS_CLK_RST_CTRL	(NNP_SYS_APB_REG_BASE + 0x0)
#define REG_EMMC_CLK_RST_CTRL0	(NNP_SYS_APB_REG_BASE + 0x200)
#define REG_EMMC_CLK_RST_CTRL1	(NNP_SYS_APB_REG_BASE + 0x204)
#define REG_EMMC_CARD_PAD_SEL	(NNP_SYS_APB_REG_BASE + 0x208)
#define REG_EMMC_PHY_TEST0  	(NNP_SYS_APB_REG_BASE + 0x20c)
#define REG_EMMC_PHY_TEST1  	(NNP_SYS_APB_REG_BASE + 0x210)
#define REG_EMMC_REG0       	(NNP_SYS_APB_REG_BASE + 0x214)

#define REG_EMMC_PHY_VERSION_ID    (EMMC_PHY_REG_BASE + 0x00)
#define REG_EMMC_PHY_INT_EN        (EMMC_PHY_REG_BASE + 0x04)
#define REG_EMMC_PHY_INT_SRC       (EMMC_PHY_REG_BASE + 0x08)
#define REG_EMMC_PHY_CTRL          (EMMC_PHY_REG_BASE + 0x0C)
#define REG_EMMC_PHY_TEST_O        (EMMC_PHY_REG_BASE + 0x10)
#define REG_EMMC_PHY_TEST_I        (EMMC_PHY_REG_BASE + 0x14)
#define REG_EMMC_PHY_IE_CTRL       (EMMC_PHY_REG_BASE + 0x18)
#define REG_EMMC_PHY_DL_CTRL       (EMMC_PHY_REG_BASE + 0x1C)
#define REG_EMMC_PHY_INT_MASK      (EMMC_PHY_REG_BASE + 0x20)
#define REG_EMMC_PHY_CTRL2         (EMMC_PHY_REG_BASE + 0x24)



#define SDIO0_CLK_RST_CTRL		(NNP_SYS_APB_REG_BASE+0x500)

#define	AXI_SDIO0_EN			BIT(5)
#define	SDIO0_CLK_SEL			(0x3 << 3)
#define	SDIO0_SOFT_RST			BIT(2)
#define	SDIO0_DLLREF_EN			BIT(1)
#define	SDIO0_EN		    	BIT(0)

#define SDIO0_CTRL0				(NNP_SYS_APB_REG_BASE + 0x504)
#define SDIO0_CTRL1				(NNP_SYS_APB_REG_BASE + 0x508)
#define SDIO0_DLLINCTRLREG_SPL	(NNP_SYS_APB_REG_BASE + 0x50c)
#define SDIO0_DLLININFOREG_SPL	(NNP_SYS_APB_REG_BASE + 0x510)
#define SDIO0_DLLOUTREG_SPL		(NNP_SYS_APB_REG_BASE + 0x514)
#define SDIO0_DLLINCTRLREG_DRV	(NNP_SYS_APB_REG_BASE + 0x518)
#define SDIO0_DLLININFOREG_DRV	(NNP_SYS_APB_REG_BASE + 0x51c)
#define SDIO0_DLLOUTREG_DRV		(NNP_SYS_APB_REG_BASE + 0x520)

#define CK_CTRL0				(VDU_SYS_APB_REG_BASE + 0x0)
#define	SDIO1_CLK_SEL			(0x3 << 18)
#define	SDIO1_DLLREF_EN			BIT(21)
#define	SDIO1_EN		    	BIT(20)

#define CK_CTRL2				(VDU_SYS_APB_REG_BASE + 0x8)
#define	AXI_SDIO1_EN			BIT(10)

#define SOFT_RST0				(VDU_SYS_APB_REG_BASE + 0x64)
#define	SDIO1_SOFT_RST			BIT(18)

#define SDIO1_CTRL0				(VDU_SYS_APB_REG_BASE + 0x124)
#define SDIO1_DLLINCTRLREG_SPL	(VDU_SYS_APB_REG_BASE + 0x128)
#define SDIO1_DLLININFOREG_SPL	(VDU_SYS_APB_REG_BASE + 0x12c)
#define SDIO1_DLLOUTREG_SPL		(VDU_SYS_APB_REG_BASE + 0x130)
#define SDIO1_DLLINCTRLREG_DRV	(VDU_SYS_APB_REG_BASE + 0x134)
#define SDIO1_DLLININFOREG_DRV	(VDU_SYS_APB_REG_BASE + 0x138)
#define SDIO1_DLLOUTREG_DRV		(VDU_SYS_APB_REG_BASE + 0x13c)
#define SDIO1_CTRL1				(VDU_SYS_APB_REG_BASE + 0x148)




enum DMA_HW_HS_MAP
{
    UART0_RX,
    UART0_TX,
    UART1_RX,
    UART1_TX,
    UART2_RX,
    UART2_TX,
    UART3_RX,
    UART3_TX,
    UART4_RX,
    UART4_TX,
    UART5_RX,
    UART5_TX,
    I2C0_RX,
    I2C0_TX,
    I2C1_RX,
    I2C1_TX,
    I2C2_RX,
    I2C2_TX,
    I2C3_RX,
    I2C3_TX,
    I2C4_RX,
    I2C4_TX,
    I2C5_RX,
    I2C5_TX,
    I2S0_RX,
    I2S0_TX,
    AES_RX,
    AES_TX,
    SPI1_RX,
    SPI1_TX,
    SPI2_RX,
    SPI2_TX,
    SPI0_RX,
    SPI0_TX,
    SRC_RX,
    SRC_TX,
    HASH_RX,
    HKEY_RX,
    RSA_RX,
    ACODEC_TX,
    ACODEC_RX,
    DMA_HW_HS_END,
};


struct s_train_val{
	unsigned char *name;
	unsigned int src_add;
	unsigned int src_mask;
	unsigned int src_vaild_index;
	unsigned char *dst_base_name;
	unsigned int dst_add;
	unsigned int dst_vaild_index;
	unsigned int *bind_train_array;
	unsigned int bind_train_size;
	int usr_train_offset;
};

struct gmac_plat_info{
	unsigned int regs;
	unsigned int id;
#define MAX_PHY_DRIVER_SUPPORT_SIZE	5
	char *phy_driver_list[MAX_PHY_DRIVER_SUPPORT_SIZE];
    void *p_cfg_array;
};





struct mshc_lite_emmc_card_info{

	char *mmc_name;
    char mmc_name_buf[16];
    #define FORCE_USR_SETTING   0x55aaaa55
    //default auto..
    #define AUTO_TUNING_THEN_REC  0x0
    unsigned int flag;
    #define AUTO_TUNING_DONE    0x656e6f64  //means 'done'
    unsigned int magic;
    //cpy sw para to emmc mem..
    unsigned int sup_mode;

    unsigned int es_sup;

    unsigned int hs_tx_data;
    unsigned int hs_rx_cmd;
    unsigned int hs_rx_data;

    unsigned int hs200_tx_data;
    unsigned int hs200_rx_cmd;
    unsigned int hs200_rx_data;

    unsigned int hs400_tx_data;
    unsigned int hs400_rx_cmd;
    unsigned int hs400_rx_data;
};

struct mshc_lite_plat_info{

	unsigned int id;
    char *name;
   	unsigned int ctrl_regs;
    unsigned int phy_regs;
    struct mshc_lite_emmc_card_info *emmc_info_list;
    //phy init
    void (*soc_clk_init)(void *p_rev);
    //void (*phy_init)(void *p_rev);
    void (*soc_ctrl_reset)(void *p_rev);
    void (*clk_set)(void *p_rev,unsigned int clk);
};



#define FH_GMAC_PHY_IP101G	0x02430C54
#define FH_GMAC_PHY_RTL8201	0x001CC816
#define FH_GMAC_PHY_TI83848	0xFFFFFFFF
#define FH_GMAC_PHY_INTERNAL 0x441400
#define FH_GMAC_PHY_INTERNAL_V2 0x46480000
#define FH_GMAC_PHY_RTL8211F 0x001cc916
#define FH_GMAC_PHY_MAE0621 0x7b744411
#define FH_GMAC_PHY_JL2101 0x937c4032
#define FH_GMAC_PHY_DUMMY	0xE3FFE3FF
#endif
